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(R)
TDA7449
TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER - 2 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT TREBLE, AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7449 is a volume tone (bass and treble) balance (Left/Right) processor for quality audio applications in TV systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. BLOCK DIAGRAM
MUXOUTL 10 8 100K TREBLE(L) 16
DIP20
ORDERING NUMBER: TDA7449
The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
BIN(L) BOUT(L) 15 RB 14
L-IN1
L-IN2
9 100K G VOLUME TREBLE BASS SPKR ATT LEFT
5
LOUT
R-IN1
7 100K
0/30dB 2dB STEP
19 I CBUS DECODER + LATCHES
2
20 18
SCL SDA DIG_GND
R-IN2
6 100K G VOLUME TREBLE BASS SPKR ATT RIGHT VREF
4
ROUT
2 INPUT MULTIPLEXER + GAIN 11 MUXOUTR 17 TREBLE(R) 12 SUPPLY RB 13 1 CREF 3
VS AGND
BIN(R) BOUT(R)
D98AU847A
April 1999
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TDA7449
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -10 to 85 -55 to 150 Unit V C C
PIN CONNECTION
CREF VS PGND ROUT LOUT R_IN2 R_IN1 L_IN1 L_IN2 MUXOUT(L)
1 2 3 4 5 6 7 8 9 10
D98AU848
20 19 18 17 16 15 14 13 12 11
SDA SCL DIG_GND TREBLE(R) TREBLE(L) BIN(L) BOUT(L) BOUT(R) BIN(R) MUXOUT(R)
THERMAL DATA
Symbol R th j-pin Parameter Thermal Resistance Junction-pins Value 150 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio V out = 1Vrms (mode = OFF) Channel Separation f = 1KHz Input Gain in (2dB step) Volume Control Treble Control Balance Control Mute Attenuation (1dB step) (2dB step) 1dB step 0 -47 -14 -14 -79 100 Parameter Min. 6 2 0.01 106 90 30 0 +14 +14 0 0.1 Typ. 9 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB dB dB
Bass Control (2dB step)
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TDA7449
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, RL= 10K, RG = 600, all controls flat (G = 0dB), unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection 6 60 9 7 90 10.2 V mA dB
INPUT STAGE
R IN V CL SIN Ginmin Ginman Gstep Input Resistance Clipping Level Input Separation Minimum Input Gain Maximum Input Gain Step Resolution THD = 0.3% The selected input is grounded through a 2.2 capacitor 2 80 -1 100 2.5 100 0 30 2 1 K Vrms dB dB dB dB
VOLUME CONTROL
C RANGE AVMAX ASTEP EA ET VDC Amute Control Range Max. Attenuation Step Resolution Attenuation Set Error Tracking Error DC Step Mute Attenuation AV = 0 to -24dB AV = -24 to -47dB AV = 0 to -24dB AV = -24 to -47dB adjacent attenuation steps from 0dB to AV max 80 45 45 0.5 -1.0 -1.5 47 47 1 0 0 0 0 0 0.5 100 49 49 1.5 1.0 1.5 1 2 3 dB dB dB dB dB dB dB mV mV dB
BASS CONTROL (1)
Gb BSTEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut +12.0 1 18.75 +14.0 2 25 +16.0 3 31.25 dB dB K
TREBLE CONTROL (1)
Gt TSTEP C RANGE SSTEP EA VDC Amute Control Range Step Resolution Max. Boost/cut +13.0 1 +14.0 2 +15.0 3 dB dB
SPEAKER ATTENUATORS
Control Range Step Resolution Attenuation Set Error DC Step Mute Attenuation AV = 0 to -20dB AV = -20 to -56dB adjacent attenuation steps 80 0.5 -1.5 -2 76 1 0 0 0 100 1.5 1.5 2 3 dB dB dB dB mV dB
NOTE1: 1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does't reset the device. 2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
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TDA7449
ELECTRICAL CHARACTERISTICS (continued.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
AUDIO OUTPUTS
VCLIP RL RO VDC Clipping Level Output Load Resistance Output Impedance DC Voltage Level d = 0.3% 2.1 2 10 2.6 40 3.8 70 VRMS K V V dB dB dB dB %
GENERAL
ENO Et S/N SC d Output Noise Total Tracking Error Signal to Noise Ratio Channel Separation Left/Right Distortion All gains = 0dB; BW = 20Hz to 20KHz flat AV = 0 to -24dB AV = -24 to -47dB All gains 0dB; VO = 1VRMS ; 80 AV = 0; VI = 1VRMS ; 5 0 0 106 100 0.01 15 1 2
0.08
BUS INPUT
V IL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge 1 VIN = 0.4V IO = 1.6mA 3 -5 0.4 5 0.8 V V A V
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TDA7449
P.C.Board
TEST CIRCUIT
C9 5.6nF J5 IN1L J3 RCA 1 2 J4 3 4 5 CON3 IN1R J2 RCA 0/30dB 2dB STEP GND IN1L GND IN2L GND L-IN1 C3 0.47F L-IN2 C4 0.47F 9 100K G VOLUME TREBLE 8 100K MUXOUTL 10 TREBLE(L) 16
R2 2K 150nF 330nF
C7 BIN(L) 15 RB
C8 BOUT(L) 14 OUT_L 1 2 3 4 CON4 +9 V JP1 JUMPER OUT_R
J8
J9
OUT_L 5 LOUT BASS SPKR ATT LEFT OUT_ R
J10
18 I2CBUS DECODER + LATCHES 19 20
DIG_GND SCL SDA
1 2 3 4 CON4 J6
1 J1 2 3 4 CON
IN2R GND IN1R GND
R-IN2 C1 0.47F R-IN1 C2 0.47F
6 100K 7 VREF 100K 3 INPUT MULTIPLEXER + GAIN SUPPLY RB 11 MUXOUTR TREBLE(R) 17 BIN(R) 12 BOUT(R) C5 C6 13 1 CREF 2 AGND VS +9V +V8 GND R3 30 C13 100nF SPKR ATT RIGHT 4 ROUT
G
VOLUME
TREBLE
BASS
C12 22F 1 2 CON2 J7
1 J5 2 3 4 CON4
MOUTL GND MOUTR GND
C10 5.6nF
150nF R1
330nF 2K
C11 10F
D98AU849A
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TDA7449
APPLICATION SUGGESTIONS The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7449 audioprocessor provides 2 bands tones control. Bass, Stages The Bass cell has an internal resistor Ri = 25K typical. Several filter types can be implemented, connecting external components to the Bass IN and OUT pins. The fig.1 refers to basic T Type Bandpass Filter starting from the filter component values (R1 inFigure 1. ternal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows: FC =
1 2 Ri, R2, C1, C2 R2 C2 + R2 C1 + Ri C1
R2 C1 + R2 C2 Ri R2 + C1 C2 R2 C1 + R2 C2
AV =
Q=
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be: C1 = AV - 1 2 Ri Q C2 = Q2 C1 (AV - 1) Q2
R2 =
AV - 1 - Q2 2 C1 FC (AV - 1) Q
Ri internal IN C1 R2
D95AU313
OUT C2
Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25K typical) and an external capacitor connected between treble pins and ground Typical responses are reported in Figg. 10 to 13. CREF The suggested 10F reference capacitor (CREF) value can be reduced to 4.7F if the application requires faster power ON.
Figure 2: THD vs. frequency
Figure 3: THD vs. RLOAD
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TDA7449
Figure 4: Channel separation vs. frequency Figure 5: Bass response
Ri = 25k C1 = 150nF C2 = 330nF R2 = 2k
Figure 6: Treble response
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TDA7449
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7449 and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS knowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking.
Figure 4: Timing Diagram of I2CBUS
Figure 5: Acknowledge on the I2CBUS
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TDA7449
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7449 address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X
SUBADDRESS LSB X B DATA ACK MSB
DATA 1 to DATA n LSB DATA ACK P
D96AU420
ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment
EXAMPLES No Incremental Bus The TDA7449 receives a start condition, the cor-
rect chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X
SUBADDRESS LSB X 0 D3 D2 D1 D0 ACK MSB
DATA LSB DATA ACK P
D96AU421
Incremental Bus The TDA7449 receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas
SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X
SUBADDRESS LSB X 1 D3 D2 D1 D0 ACK MSB
DATA 1 to DATA n LSB DATA ACK P
D96AU422
9/17
TDA7449
POWER ON RESET CONDITION
INPUT SELECTION INPUT GAIN VOLUME BASS TREBLE SPEAKER IN2 28dB MUTE 2dB 2dB MUTE
DATA BYTES Address = 88 HEX (ADDR:OPEN). FUNCTION SELECTION: First byte (subaddress)
MSB D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 B B B B B B B B D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SUBADDRESS INPUT SELECT INPUT GAIN VOLUME NOT ALLOWED BASS TREBLE SPEAKER ATTENUATE "R" SPEAKER ATTENUATE "L"
B = 1: INCREMENTAL BUS ACTIVE B = 0: NO INCREMENTAL BUS X = DON'T CARE
INPUT SELECTION
MSB D7 X X X X D6 X X X X D5 X X X X D4 X X X X D3 X X X X D2 X X X X D1 0 0 1 1 LSB D0 0 1 0 1 INPUT MULTIPLEXER NOT ALLOWED NOT ALLOWED IN2 IN1
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TDA7449
DATA BYTES (continued) INPUT GAIN SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
GAIN = 0 to 30dB
LSB D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
INPUT GAIN 2dB STEPS 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB 22dB 24dB 26dB 28dB 30dB
VOLUME SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 X
VOLUME = 0 to 47dB/MUTE
LSB D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1
VOLUME 1dB STEPS 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 0dB -8dB -16dB -24dB -32dB -40dB
0 0 0 0 1 1 1
0 0 1 1 0 0 1
0 1 0 1 0 1 1 X X X
MUTE
11/17
TDA7449
DATA BYTES (continued) BASS SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 BASS 2dB STEPS -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
TREBLE SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 TREBLE 2dB STEPS -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
12/17
TDA7449
DATA BYTES (continued) SPEAKER ATTENUATE SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 X X X D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER ATTENUATION 1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB -64dB -72dB MUTE
SPEAKER ATTENUATION = 0 to -79dB/MUTE
PIN: 1
PINS: 4, 5
VS
VS
VS 20K
ROUT LOUT 24
CREF 20K
20A
D96AU430
D96AU434
13/17
TDA7449
PINS: 6,7,8,9 PINS: 10,11
VS 20A
MUXOUT
VS
VS 20A
IN
100K
GND
VREF
D96AU425
D96AU491
PINS: 12, 15
VS 20A
PINS: 13, 14
VS 20A
25K BIN(L) BIN(R)
D98AU850
44K BOUT(L) BOUT(R)
D96AU429
PINS: 16, 17
PIN: 19
VS 20A TREBLE(L) TREBLE(R) 50K
20A SCL
D96AU433
D96AU424
14/17
TDA7449
PIN: 20
20A SDA
D96AU423
15/17
TDA7449
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX.
DIM.
OUTLINE AND MECHANICAL DATA
DIP20
0.053
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TDA7449
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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